Champéry Winter School 2020

The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM and flash technologies are experiencing difficult technology scaling challenges that make the maintenance and enhancement of their capacity, energy efficiency, performance, and reliability significantly more costly with conventional techniques. In fact, recent reliability issues with DRAM, such as the RowHammer problem, are already threatening system security and predictability. We are at the challenging intersection where issues in memory reliability and performance are tightly coupled with not only system cost and energy efficiency but also system security.

In this tutorial, we first discuss major challenges facing modern memory systems (and the computing platforms we currently design around the memory system) in the presence of greatly increasing demand for data and its fast analysis. We then examine some promising research and design directions to overcome these challenges. We discuss at least three key topics in some detail, focusing on both open problems and potential solution directions:

1. fundamental issues in memory reliability and security and how to enable fundamentally secure, reliable, safe architectures
2. enabling data-centric and hence fundamentally energy-efficient architectures that are capable of performing computation near data
3. reducing both latency and energy consumption by tackling the fixed-latency/energy mindset

If time permits, we will also discuss research challenges and opportunities in enabling emerging NVM (non-volatile memory) technologies and scaling NAND flash memory and SSDs (solid state drives) into the future.

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and hardware security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online. For more information, please see his [webpage](https://people.inf.ethz.ch/omutlu/).

High-level synthesis (HLS) tools create dedicated circuits from languages such as C and, thus, appear to promise to make hardware design accessible, among others, to software programmers targeting configurable platforms. Unfortunately, this is generally not quite the case: commercial and academic HLS tools almost universally need expert guidance; users must understand the nature of the circuits generated to restructure the input C code or add pragmas and thus force synthesis tools to generate the desired output. Partly, this significant shortcoming depends by the very nature of the traditional HLS process: tools almost universally generate statically scheduled datapaths and this implies that circuits out of HLS tools have a hard time exploiting parallelism to the limits hardware designers expect. While in many cases code refactoring and pragmas to the HLS tools solve the problem, when addressing code with potential memory dependencies, with control-dependent dependencies in inner loops, or where performance is limited by long latency control decisions, classic HLS tools just fail to produce competitive hardware. Recently, there has been some interest in generating dynamically scheduled circuits instead (somehow analogous to out-of-order superscalar processors in the software programmable world); such new HLS techniques may become critical in coming years if broader application classes will need the benefits of reconfigurable hardware acceleration. In this lecture, we start by reviewing the basic notions of classic HLS and develop a basic understanding of how tools generate circuits--and, therefore, of their fundamental limitations. We discuss through examples some of the code restructuring such tools need. Then, we describe our experiences with dynamically scheduled dataflow circuits: we present a generic methodology to generate them from C programs, contrast their operation to traditional HLS results, discuss some of their specific challenges, and outline the opportunities they create for results that are more friendly to software code. (Joint work with Lana Josipović, Andrea Guerrieri, et al.)

Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th and at the 24th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012 and 2016, at the 19th International Conference on Field-Programmable Logic and Applications (FPL), in 2009, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.

Computing capability is the key factor for AI. And the AI chip is thought as the engine of AI computing capability. The AI chip, especially the AI chip for data center, is a full stack system, including product definition, algorithm, software, architecture and VISI implementation. In this talk, I will talk about the challenges and my perspectives of building a AI chip.

Jian Ouyang, Baidu Distinguished Architect, is the head of Baidu AI silicon department. He is working on AI chip product, architecture and system. He had published several papers on ASPLOS2014, Hotchips2014/2016/2017 and so on.

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